The present invention relates to semiconductor memory devices, and more particularly, to write data input circuits used in semiconductor memory devices such as double data rate (DDR) SDRAMs.
DDR SDRAMs have been proposed in recent years to further increase the data transmission rate.
A conventional SDRAM acquires an external command in synchronism with a clock signal. If the external command is, for example, a write command, the prior art SDRAM receives the corresponding write data in synchronism with the rising edge of the clock signal.
In contrast, the DDR SDRAM acquires the write data in synchronism with both the rising and falling edges of a data strobe signal. More specifically, the DDR SDRAM acquires the write command in synchronism with the clock signal, and then receives the write data in synchronism with the rising edge of the data strobe signal. The data strobe signal is output at around the time when the clock signal following the clock signal which acquires the write command goes high. Accordingly, the DDR SDRAM acquires the write data at a transmission rate which is two times faster than that of the conventional SDRAM.
FIG. 1 is a schematic block diagram showing the DDR SDRAM 100. As shown in FIG. 1, the DDR SDRAM 100 includes an external command input buffer 51, an external command latch circuit 52, a clock signal input buffer 53, a command decoder 54, an internal command latch circuit 55, a data strobe signal input buffer 56, a data input buffer 57, a first data latch circuit 58, and a second data latch circuit 59.
The external command input buffer 51 receives an external command COM from an external device (not shown) and provides the external command COM to the external command latch circuit 52. The external command latch circuit 52 latches the external command COM in synchronism with the rising of the clock signal provided from the clock signal input buffer 53.
The latched command COM is decoded by the command decoder 54. The decoded command COM is latched by the internal command latch circuit 55 as an internal command and provided to an internal circuit.
If the latched internal command is a write command, the internal command latch circuit 55 provides the data strobe signal input buffer 56 and the data input buffer 57 with an enable signal WRTZ. The data strobe signal input buffer 56 is activated in response to the enable signal WRTZ, receives a data strobe signal DQS having a rectangular wave from an external device, and provides the first and second data latch circuits 58, 59 with the data strobe signal DQS.
The data input buffer 57 is also activated by the enable signal WRTZ. The data input buffer 57 sequentially receives write data DQ (D1, D2) from an external device and provides the first and second data latch circuits 58, 59 with the write data DQ (D1, D2) in accordance with the rising and falling edges of the data strobe signal DQS. The first data latch circuit 58 latches the write data DQ (D1) from the data input buffer 57 in synchronism with the rising of the data strobe signal DQS. The second data latch circuit 59 latches the write data DQ (D2) from the data input buffer 57 in synchronism with the falling of the data strobe signal DQS. The latched write data D1, D2 is sent to a DRAM core circuit (not shown) and written to a memory cell at predetermined addresses.
FIG. 2 is a timing chart showing the behavior of the clock signal CLKZ and the data strobe signal DQS of the write command. As shown in FIG. 2, the external command COM is latched by the clock signal CLKZ. The data strobe signal DQS rises within a range of .+-.25% of a single cycle tCLK from the rising of the clock signal CLKZ.
In other words, when a single cycle of the clock signal CLKZ is represented as tCLK, the time between the rising of the clock signal CLKZ that latches the external command COM and the earliest rising of the data strobe signal DQS, or the minimum time tDQSSmin, is represented as tDQSSmin=0.75 tCLK (nanoseconds).
The time until the latest rising of the data strobe signal DQS, or the maximum time tDQSSmax, is represented as tDQSSmax=1.25 tCLK (nanoseconds).
If a single cycle tCLK of the clock signal CLKZ takes ten nanoseconds (the frequency of the clock signal CLKZ being 100 megahertz), the minimum time tDQSSmin and the maximum time tDQSSmax are obtained as described below. EQU tDQSSmin=0.75 tCLK=7.5 (nanoseconds) EQU tDQSSmax=1.25 tCLK=12.5 (nanoseconds)
Accordingly, the strobe signal input buffer 56 and the data input buffer 57 must be activated presuming that the data strobe signal DQS rises at the minimum time tDQSSmin.
The determination of whether the data strobe signal DQS is low prior to the rising of the strobe signal DQS must be completed by the data strobe signal input buffer 56 before the minimum time tDQSSmin (0.75 tCLK) elapses. Furthermore, since the data strobe signal input buffer 56 is generally formed by a current mirror circuit, a certain amount of time is necessary to activate the data strobe signal input buffer 56 from a deactivated state.
The time necessary for the data strobe input buffer 56 to determine whether the data strobe signal DQS is low can be represented as T11, and the time necessary for activating the data strobe signal input buffer 56 can be represented as T12. In this case, at least time T11+T12 is necessary prior to the rising of the data strobe signal DQS when the data strobe signal input buffer 56 receives the enable signal WRTZ.
In other words, at least a first guarantee time Ta is necessary from when the clock signal CLK, which latched the write command, rises to when the enable signal WRTZ rises. This can be represented as Ta=0.75 tCLK--(T11+T12) (nanoseconds).
If a single cycle tCLK of the clock signal CLKZ takes ten nanoseconds, the first guarantee time Ta is obtained as described below. EQU Ta=7.5-(T11+T12)(nanoseconds)
The setup time of the first and second data latch circuits 58, 59 must be provided for between the activation of the data input buffer 57 and the rising of the data strobe signal DQS. Furthermore, in the same manner as the data strobe signal input buffer 56, the data input buffer 57 is generally formed by a current mirror circuit and requires a certain amount of time before activation.
The setup time of the first and second data latch circuits 58, 59 may be represented as T21 and the time necessary for activating the data input buffer 57 may be represented as T22. In this case, at least time T21+T22 is necessary prior to the rising of the data strobe signal DQS when the data input buffer 57 receives the enable signal WRTZ.
In other words, at least a second guarantee time Tb is necessary from when the clock signal CLK, which latched the write command, rises to when the enable signal WRTZ rises. This can be represented as Tb=0.75 tCLK-(T21+T22) (nanoseconds).
If a single cycle tCLK of the clock signal CLKZ takes ten nanoseconds, the second guarantee time Tb is obtained as described below. EQU Tb=7.5-(T21+T22)(nanoseconds)
The time from when the clock signal CLK, which has latched the write command, rises to when the enable signal WRTZ is output, or the accumulated delay time Tc, is determined by a delay time T31 of the external command input buffer 51 and the clock signal input buffer 53, a latching time T32 of the external command latch circuit 52, a decoding time T33 of the command decoder 54, and the latching time T34 of the internal command latch circuit 55.
In other words, the accumulated delay time Tc can be represented as Tc=T31+T32+T33+T34 (nanoseconds).
If T11 takes 0.5 nanoseconds and T12 takes 1.5 nanoseconds when a single cycle of the clock signal CLKZ takes ten nanoseconds (the frequency being 100 megahertz), the first guarantee time Ta is obtained as described below. EQU Ta=7.5-(0.5+1.5)=5.5 (nanoseconds)
If T21 takes 0.5 nanoseconds and T22 takes 1.5 nanoseconds, the second guarantee time is obtained as described below. EQU Tb=7.5-(0.5+1.5)=5.5 (nanoseconds)
Furthermore, if T31 through T33 each take two nanoseconds, and if T34 takes one nanosecond, the accumulated time Tc is obtained as described below. EQU Tc=2+2+2+1=7
Accordingly, there is a relationship of Tc&gt;Ta and Tc&gt;Tb.
In other words, the enable signal WRTZ is provided to the data strobe signal input buffer 56 and the data input buffer 57 with a delay of 1.5 nanoseconds from the first and second guarantee time Ta, Tb (5.5 nanoseconds). As a result, the input buffers 56, 57 may not be able to acquire the write date D1 in response to the rising of the data strobe signal DQS.
For guaranteed operation, each of the input buffers 56, 57 and the data latch circuits 58, 59 are activated prior to the first and second guarantee time Ta, Tb. More specifically, the input buffers 56, 57 and the data latch circuits 58, 59 are activated in response to an activate command provided by an external device before the write command is provided The activate command is provided a few clock signals before the write command. Thus, the operation is guaranteed since the input buffers 56, 57 and the data latch circuit 58, 59 are activated with a margin.
However, since the input buffers 56, 57 and the data latch circuits 58, 59 are activated a few clock signals before the write command, unnecessary current flows through the input buffers 56, 57 and the data latch circuits 58, 59. Further, the input buffers 56, 57 and the data latch circuit 58, 59 are always activated in response to the activate command even if the write command is not provided. Thus, unnecessary current is continuously consumed.